1. Field of the Disclosure
The present disclosure generally relates to the fabrication of integrated circuits, and more particularly, to various methods for forming source/drain contacts during CMOS integration and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, Metal-Oxide-Semiconductor (MOS) technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit either a high conductive state (on-state) or a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region of the device.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET device, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form what is sometimes referred to as a “tri-gate” structure, such that the channel has a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin, in which case the FinFET device only has what is sometimes referred to as a “dual-gate” structure. Unlike a planar FET, in a FinFET device, the channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2x) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is generally a superior MOSFET structure as compared to that of a typical planar FET, especially in aggressively sized devices, such as the 20/22 nm Complementary MOS (CMOS) technology node and beyond.
By using such field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, embedded memories and the like. Over the recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density” in such products has been commensurately increased. Such improvements in the performance of transistor devices has reached the point where the limiting factor of the finally achieved operating speed of complex integrated circuit products is not always based solely on the individual transistor element configuration(s), but is instead often a function of the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but generally require a metallization system that includes one or more metallization layers that are positioned above the device level. Typically, a metallization layer includes a plurality of conductive structures that are embedded in a layer of dielectric insulating material, and are generally one of two types. “Intra-level” connections are substantially horizontal metal-containing structures—sometimes referred to as “lines”—that provide electrical connections within a given metallization layer. “Inter-level” connections are substantially vertical metal-containing structures—sometimes referred to as vias—that provide electrical connections between the various adjacent stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical device level contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the first metallization layer. In some applications, the second end of the contact structure may be connected to a contact region of a further semiconductor-based circuit element, in which case the interconnect structure in the contact level between the device level and the overlying metallization system is also referred to as a local interconnect. The contact structure may include contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. As the critical dimensions of the circuit elements in the device level have decreased, the dimensions of metal lines, vias and contact elements have also been reduced. In some cases, the increased packing density has mandated the use of sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with the desired circuit element density in the device level.
As device dimensions have decreased, e.g., transistors with gate lengths of 50 nm and less, the contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements, e.g., source regions, drain regions, and/or gate electrodes, and the like. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
For this reason, contact technologies have been developed in which contact openings are formed in a “self-aligned” fashion by removing the interlayer dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, the gate electrode structures are used as etch masks for selectively removing the interlayer dielectric material in order to expose the contact regions of the transistors, thereby providing self-aligned trenches which are substantially laterally delineated by the spacer structures of the gate electrode structures. Consequently, a corresponding lithography process only needs to define a global contact opening above an active region, and the contact trenches then result from the selective etch process using the gate electrode structures, i.e., the portions exposed by the global contact opening, as an etch mask. Thereafter, an appropriate contact material, such as tungsten and the like, may be filled into the contact trenches that are formed in this manner.
While the use of self-aligned contact elements has generally led to a reduction in some types of device defects and/or increased product yield, other processing-related issues and defects are sometimes associated with the use of typical contact self-alignment techniques as MOSFET devices are continuously being aggressively scaled. For example, as transistor devices become smaller and packing density increases, the space available between gate electrode structures to form the sidewall spacers that electrically isolate the self-aligned contact elements from the gate electrodes also becomes commensurately smaller, often resulting in spacers having a nominal thickness on the order of approximately 10 nm or even less. Due to such reduced spacer thicknesses, device designers have turned more to the use of low-k dielectric materials for sidewall spacer construction, rather than a more traditional silicon nitride material. However, in light of the very small target sidewall spacer thicknesses on such devices, very tight processing controls over the final spacer thickness is often necessary in order to minimize detrimental variations in the parasitic capacitance between contact elements and gate electrodes, and/or the threshold voltage of the resulting devices. Furthermore, while the type of etching processes that are used to form such self-aligned contact openings may be adapted to selectively remove the interlayer dielectric material from between gate electrode structures relative to the material of the sidewall spacers, it should be understood that such selective etching processes will also often remove at least some portion of the spacer material, albeit at a lower etch rate than that of the interlayer dielectric material. As such, the final thickness of the sidewall spacers can very often be affected during self-aligned contact formation, which can ultimately affect the parasitic capacitance and/or threshold voltage of the device.
In some prior art processing schemes, a substantially anisotropic, or directional, etching process, such as reactive ion etching (RIE) process and the like, is used to selectively remove the interlayer dielectric material from between the sidewall spacers, thus minimizing to some degree the amount of spacer thickness reduction that occurs when forming the self-aligned contact openings. However, the RIE process often damages the upper surface of the contact regions, e.g., the source/drain regions, that are exposed by the etching process. Such surface damage from an REI process can adversely affect the Schottky barrier height at the metal/semiconductor interface between the contact element and the transistor contact regions, thus potentially creating a rectifying contact where an ohmic contact is otherwise generally desired. Furthermore, a higher Schottky barrier height for the metal/semiconductor contacts of PMOS devices can be particularly problematic, as the p-type metal of PMOS contact elements typically has a relatively high Schottky barrier height, which can thus lead to a greater overall resistance between the conductive metal of the contact elements and the contact regions of the transistor device.
Another problem associated with the continued aggressive scaling of transistor devices is that the electrical resistance between the conductive contacts and the transistor element can have a greater influence on the overall electrical resistance of the device. Traditionally, low resistance metal silicide layers are formed in the underlying silicon or epitaxially grown semiconductor material of the source/drain regions of a device. Ideally, one could simply increase the contact area between the low-resistance metal silicide layer and the underlying silicon or epitaxially grown semiconductor material. However, such an approach can become problematic in the case of aggressively scaled FinFET devices, as the spacing between fins can often be quite small, such as on the order of about 15 nm or less, which leaves a very small process margin for most conventional source/drain epitaxial material growth schemes. In such cases, and considering all of the material overlay and critical dimension variations that may be associated with the device processing, the conventional epitaxial schemes cannot be reliably used to provide any more than approximately 10 nm of epitaxial growth thickness on the fins, otherwise the risk for creating an electric short between the epi material on adjacent fins (junction to channel)—i.e., fin merger—may be too great. However, such a relatively thin (e.g., approximately 10 nm or less) epi layer results in a very small volume of epi material being formed on each fin, a situation which can tend to lower the area available for silicide formation and thus increase the overall resistance at the metal/semiconductor contact interface. Furthermore, such a thin epi material layer may be substantially consumed during the silicide formation process and/or damaged during the contact etch step.
The present disclosure is generally directed to various methods for forming source/drain contacts so as to substantially avoid, or at least reduce, the effects of one or more of the problems identified above.